##################################################################
# CHECK VIVADO VERSION
##################################################################

set scripts_vivado_version 2018.3
set current_vivado_version [version -short]

if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
  catch {common::send_msg_id "IPS_TCL-100" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_ip_tcl to create an updated script."}
  return 1
}

##################################################################
# START
##################################################################

# To test this script, run the following commands from Vivado Tcl console:
# source ips.tcl
# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./XCKU115_VPX0704/WB_DEMO.xpr> in the current working folder.

set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
  create_project WB_DEMO XCKU115_VPX0704 -part xcku115-flvf1924-2-i
  set_property target_language Verilog [current_project]
  set_property simulator_language Mixed [current_project]
}

##################################################################
# CHECK IPs
##################################################################

set bCheckIPs 1
set bCheckIPsPassed 1
if { $bCheckIPs == 1 } {
  set list_check_ips { xilinx.com:ip:clk_wiz:6.0 xilinx.com:ip:axis_data_fifo:2.0 xilinx.com:ip:axis_dwidth_converter:1.1 xilinx.com:ip:gig_ethernet_pcs_pma:16.1 xilinx.com:ip:tri_mode_ethernet_mac:9.0 }
  set list_ips_missing ""
  common::send_msg_id "IPS_TCL-1001" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."

  foreach ip_vlnv $list_check_ips {
  set ip_obj [get_ipdefs -all $ip_vlnv]
  if { $ip_obj eq "" } {
    lappend list_ips_missing $ip_vlnv
    }
  }

  if { $list_ips_missing ne "" } {
    catch {common::send_msg_id "IPS_TCL-105" "ERROR" "The following IPs are not found in the IP Catalog:\n  $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
    set bCheckIPsPassed 0
  }
}

if { $bCheckIPsPassed != 1 } {
  common::send_msg_id "IPS_TCL-102" "WARNING" "Will not continue with creation of design due to the error(s) above."
  return 1
}

##################################################################
# CREATE IP UDP_pll
##################################################################

set clk_wiz UDP_pll
create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name $clk_wiz

set_property -dict { 
  CONFIG.USE_PHASE_ALIGNMENT {true}
  CONFIG.SECONDARY_SOURCE {Single_ended_clock_capable_pin}
  CONFIG.CLKOUT2_USED {true}
  CONFIG.CLKOUT3_USED {true}
  CONFIG.NUM_OUT_CLKS {3}
  CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {200.000}
  CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {15.625}
  CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {150.000}
  CONFIG.CLKOUT1_DRIVES {Buffer}
  CONFIG.CLKOUT2_DRIVES {Buffer}
  CONFIG.CLKOUT3_DRIVES {Buffer}
  CONFIG.CLKOUT4_DRIVES {Buffer}
  CONFIG.CLKOUT5_DRIVES {Buffer}
  CONFIG.CLKOUT6_DRIVES {Buffer}
  CONFIG.CLKOUT7_DRIVES {Buffer}
  CONFIG.RESET_PORT {resetn}
  CONFIG.MMCM_DIVCLK_DIVIDE {1}
  CONFIG.MMCM_CLKFBOUT_MULT_F {7.500}
  CONFIG.MMCM_CLKOUT0_DIVIDE_F {3.750}
  CONFIG.MMCM_CLKOUT1_DIVIDE {48}
  CONFIG.MMCM_CLKOUT2_DIVIDE {5}
  CONFIG.RESET_TYPE {ACTIVE_LOW}
  CONFIG.CLKOUT1_JITTER {125.501}
  CONFIG.CLKOUT1_PHASE_ERROR {116.405}
  CONFIG.CLKOUT2_JITTER {209.132}
  CONFIG.CLKOUT2_PHASE_ERROR {116.405}
  CONFIG.CLKOUT3_JITTER {132.464}
  CONFIG.CLKOUT3_PHASE_ERROR {116.405}
} [get_ips $clk_wiz]

##################################################################

##################################################################
# CREATE IP axis_data_fifo_0
##################################################################

set axis_data_fifo axis_data_fifo_0
create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name $axis_data_fifo

set_property -dict { 
  CONFIG.TDATA_NUM_BYTES {8}
  CONFIG.TUSER_WIDTH {1}
  CONFIG.FIFO_MODE {2}
  CONFIG.HAS_TKEEP {1}
  CONFIG.HAS_TLAST {1}
  CONFIG.HAS_WR_DATA_COUNT {1}
  CONFIG.HAS_RD_DATA_COUNT {1}
} [get_ips $axis_data_fifo]

##################################################################

##################################################################
# CREATE IP axis_data_fifo_1
##################################################################

set axis_data_fifo axis_data_fifo_1
create_ip -name axis_data_fifo -vendor xilinx.com -library ip -version 2.0 -module_name $axis_data_fifo

set_property -dict { 
  CONFIG.TDATA_NUM_BYTES {8}
  CONFIG.TUSER_WIDTH {1}
  CONFIG.IS_ACLK_ASYNC {1}
  CONFIG.HAS_TKEEP {1}
  CONFIG.HAS_TLAST {1}
  CONFIG.SYNCHRONIZATION_STAGES {2}
  CONFIG.HAS_WR_DATA_COUNT {1}
  CONFIG.HAS_RD_DATA_COUNT {1}
} [get_ips $axis_data_fifo]

##################################################################

##################################################################
# CREATE IP axis_dwidth_converter_0
##################################################################

set axis_dwidth_converter axis_dwidth_converter_0
create_ip -name axis_dwidth_converter -vendor xilinx.com -library ip -version 1.1 -module_name $axis_dwidth_converter

set_property -dict { 
  CONFIG.S_TDATA_NUM_BYTES {8}
  CONFIG.M_TDATA_NUM_BYTES {1}
  CONFIG.HAS_TLAST {1}
  CONFIG.HAS_TKEEP {1}
} [get_ips $axis_dwidth_converter]

##################################################################

##################################################################
# CREATE IP axis_dwidth_converter_1
##################################################################

set axis_dwidth_converter axis_dwidth_converter_1
create_ip -name axis_dwidth_converter -vendor xilinx.com -library ip -version 1.1 -module_name $axis_dwidth_converter

set_property -dict { 
  CONFIG.M_TDATA_NUM_BYTES {8}
  CONFIG.HAS_TLAST {1}
  CONFIG.HAS_TKEEP {1}
  CONFIG.HAS_MI_TKEEP {1}
} [get_ips $axis_dwidth_converter]

##################################################################

##################################################################
# CREATE IP clk_wiz_0
##################################################################

set clk_wiz clk_wiz_0
create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name $clk_wiz

set_property -dict { 
  CONFIG.USE_PHASE_ALIGNMENT {true}
  CONFIG.PRIM_IN_FREQ {50.000}
  CONFIG.SECONDARY_SOURCE {Single_ended_clock_capable_pin}
  CONFIG.CLKIN1_JITTER_PS {200.0}
  CONFIG.CLKOUT2_USED {true}
  CONFIG.CLKOUT3_USED {true}
  CONFIG.CLKOUT4_USED {false}
  CONFIG.CLKOUT5_USED {false}
  CONFIG.NUM_OUT_CLKS {3}
  CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {50.000}
  CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {100.000}
  CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {10.000}
  CONFIG.CLKOUT5_REQUESTED_OUT_FREQ {5.000}
  CONFIG.PRIM_SOURCE {Single_ended_clock_capable_pin}
  CONFIG.CLKOUT1_DRIVES {Buffer}
  CONFIG.CLKOUT2_DRIVES {Buffer}
  CONFIG.CLKOUT3_DRIVES {Buffer}
  CONFIG.CLKOUT4_DRIVES {Buffer}
  CONFIG.CLKOUT5_DRIVES {Buffer}
  CONFIG.CLKOUT6_DRIVES {Buffer}
  CONFIG.CLKOUT7_DRIVES {Buffer}
  CONFIG.USE_RESET {false}
  CONFIG.RESET_PORT {resetn}
  CONFIG.MMCM_DIVCLK_DIVIDE {1}
  CONFIG.MMCM_CLKFBOUT_MULT_F {20.000}
  CONFIG.MMCM_CLKIN1_PERIOD {20.000}
  CONFIG.MMCM_CLKIN2_PERIOD {10.0}
  CONFIG.MMCM_CLKOUT0_DIVIDE_F {20.000}
  CONFIG.MMCM_CLKOUT1_DIVIDE {10}
  CONFIG.MMCM_CLKOUT2_DIVIDE {10}
  CONFIG.MMCM_CLKOUT3_DIVIDE {1}
  CONFIG.MMCM_CLKOUT4_DIVIDE {1}
  CONFIG.RESET_TYPE {ACTIVE_LOW}
  CONFIG.CLKOUT1_JITTER {192.113}
  CONFIG.CLKOUT1_PHASE_ERROR {164.985}
  CONFIG.CLKOUT2_JITTER {162.035}
  CONFIG.CLKOUT2_PHASE_ERROR {164.985}
  CONFIG.CLKOUT3_JITTER {162.035}
  CONFIG.CLKOUT3_PHASE_ERROR {164.985}
  CONFIG.CLKOUT4_JITTER {346.083}
  CONFIG.CLKOUT4_PHASE_ERROR {155.997}
  CONFIG.CLKOUT5_JITTER {395.746}
  CONFIG.CLKOUT5_PHASE_ERROR {155.997}
} [get_ips $clk_wiz]

##################################################################

##################################################################
# CREATE IP gig_ethernet_pcs_pma_0
##################################################################

set gig_ethernet_pcs_pma gig_ethernet_pcs_pma_0
create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -version 16.1 -module_name $gig_ethernet_pcs_pma

set_property -dict { 
  CONFIG.Standard {SGMII}
  CONFIG.Management_Interface {false}
  CONFIG.SGMII_PHY_Mode {true}
  CONFIG.SupportLevel {Include_Shared_Logic_in_Core}
  CONFIG.GTinEx {false}
  CONFIG.GT_Location {X1Y16}
} [get_ips $gig_ethernet_pcs_pma]

##################################################################

##################################################################
# CREATE IP tri_mode_ethernet_mac_0
##################################################################

set tri_mode_ethernet_mac tri_mode_ethernet_mac_0
create_ip -name tri_mode_ethernet_mac -vendor xilinx.com -library ip -version 9.0 -module_name $tri_mode_ethernet_mac

set_property -dict { 
  CONFIG.Physical_Interface {Internal}
  CONFIG.MAC_Speed {1000_Mbps}
  CONFIG.Management_Frequency {125}
  CONFIG.Enable_MDIO {false}
  CONFIG.Make_MDIO_External {false}
  CONFIG.Frame_Filter {false}
  CONFIG.Number_of_Table_Entries {0}
  CONFIG.Statistics_Counters {false}
  CONFIG.Statistics_Reset {true}
} [get_ips $tri_mode_ethernet_mac]

##################################################################

